Those involved with the manufacture of high performance ultra-large scale integration (ULSI) integrated circuits must address and be sensitive to RC delay problems, cross-talk issues, and power dissipation.
RC delay is the propagation delay of a signal caused by resistance in metal lines and the capacitance between metal lines and between metal layers. RC delay is undesirable because this delay adversely affects timing requirements and the performance of the circuit design by injecting uncertainty as to when a signal will be received or valid at a particular node in the circuit. Cross-talk is the signal interference between metal lines that can adversely affect signal integrity and signal strength. Power dissipation is the dynamic power drained by unwanted capacitance charge and discharge in a circuit.
It is apparent that RC delay problems, cross-talk issues, and power dissipation stem mainly from interconnect intra-layer capacitance (i.e., capacitance between metal lines within a metal layer) and interconnect inter-layer capacitance (i.e., capacitance between metal layers). Accordingly, reducing the line-to-line (i.e., intra-layer) capacitance and inter-layer capacitance is important in reducing RC delay, cross-talk, and power dissipation in a circuit.
One approach to reduce interconnect capacitance is to utilize low dielectric constant materials (commonly referred to as “low-k” materials) in interconnect structures. Since capacitance between metal lines or layers depends directly on the dielectric constant of the material therebetween, reducing the dielectric constant reduces the capacitance. Porous materials, such as Xerogel, show promise as candidates for the low-k material because of its good thermal stability, low thermal expansion coefficient, and low dielectric constant. Unfortunately, the use of these porous materials has several disadvantages.
First, the deposition of porous materials is complicated and difficult to control. Second, the porous materials generally provide poor mechanical strength. Third, the porous materials generally provide poor thermal conductivity. Fourth, because of the porous nature of these materials, defining via holes or trenches with smooth vertical walls and bottom surfaces therein is a difficult, if not impossible, challenge. Smooth vertical walls and bottom surfaces facilitate the deposition of a continuous liner in subsequent process steps. A continuous liner is important because a non-continuous liner causes poor metal fill in the via holes or trenches that can lead to reliability problems and failure of the connection.
Another approach to reduce interconnect capacitance is to introduce air spaces between metal lines by intentionally poor-filling the gaps between the metal lines when depositing dielectric material between the metal lines. However, this approach suffers from several disadvantages. First, it is not possible to control the location of these air spaces since the location of these spaces is determined by the interconnect layout. Second, this approach does not address inter-layer capacitance since poor-filling only forms air spaces between metal lines and not between metal layers. Third, this approach goes against the principle of completely filling gaps between metal lines for better process robustness and reliability. Fourth, it is not possible to control the volume of these air spaces, since the volume of these spaces is determined by the interconnect layout. Fifth, the air volume of these gaps is usually low, resulting in relatively large effective dielectric constant, which results in higher capacitance between metal lines.
Based on the foregoing, there remains a need for an improved interconnect structure that has a low effective dielectric constant and that overcomes the disadvantages discussed previously.